Logic Gates

Logic gate definitions

class schemdraw.logic.logic.And(inputs=2, nand=False, inputnots=None, *, leadin=None, leadout=None, **kwargs)

AND gate

Parameters:

  • inputs (int) – Number of inputs to gate.

  • nand (bool) – Draw invert bubble on output

  • inputnots (Optional[Sequence[int]]) – Input numbers (starting at 1) of inputs that have invert bubble

  • leadin (Optional[float]) – Length of input leads [default: 0.35]

  • leadout (Optional[float]) – Length of output lead [default: 0.35]

Anchors:

out in[X] - for each input

class schemdraw.logic.logic.Buf(*args, **kwargs)

Buffer

Anchors:

in out

class schemdraw.logic.logic.Not(*args, **kwargs)

Not gate/inverter

Anchors:

in out

class schemdraw.logic.logic.NotNot(*args, **kwargs)

Double inverter

Anchors:

in out

class schemdraw.logic.logic.Or(inputs=2, nor=False, xor=False, inputnots=None, *, leadin=0.35, leadout=0.35, **kwargs)

OR or XOR gate element.

Parameters:

  • inputs (int) – Number of inputs to gate.

  • nor (bool) – Draw invert bubble on output

  • xor (bool) – Draw as exclusive-or gate

  • inputnots (Optional[Sequence[int]]) – Input numbers (starting at 1) of inputs that have invert bubble

  • leadin (float) – Length of input leads [default: 0.35]

  • leadout (float) – Length of output lead [default: 0.35]

Anchors:

out in[X] - for each input

class schemdraw.logic.logic.Schmitt(*args, **kwargs)

Schmitt Trigger

Anchors:

in out

class schemdraw.logic.logic.SchmittAnd(*, leadin=0.35, leadout=0.35, **kwargs)

Schmitt Trigger AND

Anchors:

in1 in2 out

class schemdraw.logic.logic.SchmittNot(*args, **kwargs)

Inverted Schmitt Trigger

Anchors:

in out

class schemdraw.logic.logic.Tgate(*args, **kwargs)

Transmission gate.

Anchors:

in out c cbar

class schemdraw.logic.logic.Tristate(outputnot=True, controlnot=False, **kwargs)

Tristate inverter :type outputnot: bool :param outputnot: Draw invert bubble on output :type controlnot: bool :param controlnot: Active-low control

Anchors:

in out c

logic_parser.logicparse(gateW=2, gateH=0.75, outlabel=None)

Parse a logic string expression and draw the gates in a schemdraw Drawing

Logic expression is defined by string using ‘and’, ‘or’, ‘not’, etc. for example, “a or (b and c)”. Parser recognizes several symbols and names for logic functions: [and, ‘&’, ‘∧’] [or, ‘|’, ‘∨’, ‘+’] [xor, ‘⊕’, ‘⊻’] [not, ‘~’, ‘¬’]

Parameters:

  • expr (str) – Logic expression

  • gateH (float) – Height of one gate

  • gateW (float) – Width of one gate

  • outlabel (Optional[str]) – Label for logic output

Return type:

Drawing

Returns:

schemdraw.Drawing with logic tree

class schemdraw.logic.table.Table(table, colfmt=None, fontsize=12, font='sans', **kwargs)

Table Element for drawing rudimentary Markdown formatted tables, such as logic truth tables.

Parameters:

  • table (str) – Table definition, as markdown string. Columns separated by |. Separator rows contain — or === between column separators.

  • colfmt (Optional[str]) – Justification and vertical separators to draw for each column, similar to LaTeX tabular environment parameter. Justification characters include ‘c’, ‘r’, and ‘l’ for center, left, and right justification. Separator characters may be ‘|’ for a single vertical bar, or ‘||’ or ‘ǁ’ for a double vertical bar, or omitted for no bar. Example: ‘cc|c’.

  • fontsize (float) – Point size of table font

  • font (str) – Name of table font

Example Table:

| A | B | Y | |—|—|—| | 0 | 0 | 1 | | 0 | 1 | 0 | | 1 | 0 | 0 | | 1 | 1 | 0 |

class schemdraw.logic.kmap.Kmap(names='ABCD', truthtable=None, groups=None, default='0', **kwargs)

Karnaugh Map

Draws a K-Map with 2, 3, or 4 variables.

Parameters:

  • names (str) – 2, 3, or 4-character string defining names of the inputs

  • truthtable (Optional[Sequence[Sequence[Union[int, str]]]]) – list defining values to display in each box of the K-Map. First element is string of 2, 3, or 4 logic 0’s and 1’s, and last element is the string to display for that input. Example: (‘0000’, ‘1’) displays a ‘1’ when all inputs are 0.

  • groups (Optional[dict]) – dictionary of style parameters for circling groups of inputs. Dictionary key must be same length as names, and defines which elements are circled using ‘0’, ‘1’, or ‘.’ in each position. For example, ‘1…’ circles every box where A=1, and ‘.11.’ circles every box where both B and C are 1. Value of dictionary pair is another dictionary containing style of box (e.g. color, fill, lw, and ls).

  • default (str) – string to display in boxes that don’t have a truthtable entry defined

Anchors:

  • cellXXXX - Center of each cell in the grid, where X is 0 or 1

class schemdraw.logic.timing.TimingDiagram(waved, **kwargs)

Logic Timing Diagram

Draw timing diagrams compatible with WaveJSON format See https://wavedrom.com/ for details. Use from_json to use WaveJSON strings copied from the site (since they can’t be copied as proper Python dicts due to lack of quoting).

Schemdraw provides a few additional extensions to the WaveJSON dictionary, including asynchronous waveforms and configuration options (color, lw) on each wave. See documentation for full specification.

Parameters:

wave – WaveJSON as a Python dict

Keyword Arguments:

  • yheight – Height of one waveform

  • ygap – Separation between two waveforms

  • risetime – Rise/fall time for wave transitions

  • fontsize – Size of label fonts

  • datafontsize – Size of data font

  • nodesize – Size of node labels

  • namecolor – Color for wave names

  • datacolor – Color for wave data text

  • nodecolor – Color for node text

  • gridcolor – Color of background grid

  • edgecolor – Color of edge notations (default blue)

  • tickcolor – Color of tick/tock labels in head/foot

  • grid – Enable grid lines (default True)

class schemdraw.logic.bitfield.BitField(reg, **kwargs)

Draw a Bit Field compatible with WaveDrom syntax. For reg parameters and examples, see https://github.com/wavedrom/bitfield.

Parameters:

  • reg (dict) – The register dictionary. See below and https://github.com/wavedrom/bitfield.

  • bitheight – Height of a bit register box in drawing units

  • width – Full width of the register box in drawing units

  • fontsize – Size of all text labels

  • lw – Line width for borders

  • ygap – Distance between lanes. Omit to auto-space based on label heights

  • vflip – Flip order of bits

  • hflip – Flip order of lanes

  • compact – Remove whitespace between lanes

The reg dictionary may have two keys. ‘reg’ is a list bitfields, and ‘config’ tha defines configuration options. Items in the reg list are dictionaries that may include:

  • name: Text to display within the bit group

  • bits: Number of bits within the group

  • attr: Label to show below the group. May be a string, or integer. If integer,

    the binary representation is shown. May also be a list of multiple lines.

  • type: 0-9 code to fill the bit group. Or may be any valid color string.

The config list may include:

  • lanes: Number of lanes (bit words stacked vertically)

  • hflip: Reverse order of lanes

  • vflip: Reverse order of bits

  • compact: Remove whitespace between lanes

  • bits: Total number of bits to include (padded out if not included in the reg list)

  • label: Dictionary of either ‘left’ or ‘right’ and text to display left or right of the lanes.

Schemdraw’s implementation has these known differences:

  • ‘type’ parameter, which is used to specify a fill color, can

    be the 0-9 code as in WaveDrom, or any valid color string

  • hspace defines the full width of the register in pixels, without including any labels

  • vspace defines the full width of a register in pixels, without including any labels or padding

  • margins are ignored (but can be set by adding the BitField to a schemdraw Drawing)